Abstract
In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis.
Highlights
Content Addressable Memories (CAM) operate by comparing data in parallel, which makes the search operation extremely fast; it makes the CAMs power hungry
We presented a thorough power characterization of matchline-based content addressable memories
We proposed a customized multi-Vdd scheme in CAMs
Summary
Content Addressable Memories (CAM) operate by comparing data in parallel, which makes the search operation extremely fast; it makes the CAMs power hungry. A post-fabrication tunable design, with variable search speeds operating over a large power-delay space, helps us adapt performance based on the workload, accommodate for process variations, and reduce design margin overheads. CAMisisaamemory memorydevice device that that performs performs two and (2)(2) It compares thethestored data with input data, in parallel across the whole chip. Most designs able stored data with input data, in parallel across the whole chip. Most CAM designs areare able to to search their entire stored data inin a single clock cycle. 1 shows the the block diagram of our search their entire stored data a single clock cycle. The main components of thechip chip are:and data anddrivers, clock drivers, rowcolumn and column decoding blocks and the core [1,2]
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
