Abstract
The ability to define patterns and fabricate structures at the nanoscale in a scalable manner is crucial not only in integrated circuit fabrication but also in fabrication of nanofluidic devices as well as in nano and micromechanical systems. Top down fabrication at the nanoscale often involves fabrication of a master using a direct write method and then its replication using a variety of methods such as by hot embossing, nanoimprint lithography, or soft lithography. Nevertheless, fabrication of the master is a time consuming and expensive process. One interesting approach is to define patterns at larger dimensions on pre-stressed films using methods such as xurography or lithography which are scalable and heat them to de-stress and shrink which can reduce the size proportionally. Although attractive, suitable fabrication processes that can perform iterative shrinking of patterns over several cycles and into the nanoscale have not been demonstrated. Here, we demonstrate a fabrication process that is capable of accurately producing patterns and features over several cycles of miniaturization and shrinking to achieve resolution in the order of 100 s of nanometers. In this approach, a pattern transfer method is developed by combining soft imprint lithography followed by reactive ion etching, both of which are scalable processes, to transfer the original patterns into a shrinkable polymer film. The patterned shrinkable film is heated to allow thermal shrinking. As a result, the pattern size was decreased by 60% of the original size in a single cycle. This reduced pattern was used as the master for the next cycle and three cycles of miniaturization was demonstrated. Sub-micron patterns of 750 nm were generated by the multi-step miniaturization method, showing approximately 20× reduction in size of the original patterns. Finally, these patterns are transferred into features on a silicon substrate to demonstrate its application in semiconductor microfabrication or its use as a master template for microsystems applications.
Highlights
reactive ion etching (RIE) patterns typically are generated using hard metal masks that are difficult to produce from the shrunk patterns generated from them for continued miniaturization
To improve the surface nish of the generated pattern which has a signi cant effect on the delity of the subsequent miniaturization steps, a silicon wafer coated with a photoresist was patterned by same so imprint lithography process using the PDMS mold formed from the shrunk pattern (Fig. 1g)
The initial master (Fig. 2a) was fabricated lithographically as a line pattern with 15 mm line width and 30 mm spacing. These dimensions were chosen as they are achievable by low cost methods such as laser writing or 3D printing using stereolithography methods
Summary
Paper of resolution in the cycle. RIE patterns typically are generated using hard metal masks that are difficult to produce from the shrunk patterns generated from them for continued miniaturization. Existing methods are suited for a single step miniaturization where the existing pattern is reduced by 30– 70% of its original size They are not ideally suited for a multi cycle miniaturization process where the shrunk pattern from the previous cycle can be used as a master for the cycle for scalable miniaturization to sub micrometer and nanometer dimensions. We report a scalable miniaturization approach using heat shrinkable Polystyrene (PS) lms that generates a proportionally miniaturized pattern which can in-turn be used as master for the cycle of miniaturization. We demonstrate that this approach can be used multiple times to fabricate submicron patterns. We applied this new capability to fabricate patterns in a silicon wafer that can be used as a functional substrate for many applications such as diffraction grating based sensors[14,15] or as a master template for so lithography applications.[16,17]
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