Multi-Standard Hybrid PLL With Low Phase-Noise Characteristics for GSM/EDGE and LTE Applications

Abstract

This paper presents a single-chip CMOS multi-standard frequency synthesizer for global system for mobile communications (GSM)/enhanced data rate for GSM evolution (EDGE) and long-term evolution (LTE) applications. Low phase-noise characteristics are achieved both in-band and out-of-band through a voltage-and-digitally controlled oscillator (VDCO) and digital calibration blocks. The proposed hybrid phase-locked loop (PLL) has two feedback loops. One is the main loop of the analog PLL and the other is a digital feedback loop used for polar modulation and digital calibrations. The digital feedback loop, nested inside the PLL, linearizes and accurately controls the tunable characteristic of the VDCO, which is important for the polar modulation. In the GSM/EDGE mode, the PLL has a 0.79 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> root-mean-square (rms) phase error and the measured phase noise is -162.5 dBc/Hz at a 20-MHz offset from an 824-MHz carrier. In the LTE mode, the measured local oscillator rms jitter is 218 fs while the PLL consumes 26.4 mW. The resulting figure of merit of the proposed PLL is -239 dB, which is superior to recent multi-standard PLLs. This multi-standard hybrid PLL is implemented in a 65-nm CMOS technology and occupies 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .