Abstract
A novel concept for a microprocessor-controlled deflection processor intended for a microprocessor-controlled TV receiver or monitor is described. This concept is implemented in an IC providing horizontal and vertical control signals, switched-mode power supply (SMPS) control pulses, and the usual identification or synchronization signals. This IC receives standard TV video signals at 16 kHz, 50/60 Hz and delivers line, field, and SMPS drive signals at the same frequency or at the doubled frequency 32 kHz, 50/60 Hz or 100/120 Hz. Doubling of line and/or field frequency is necessary in double-scanning or flicker-free TV concepts. The setting of picture geometry parameters and SMPS adjustment is accomplished by a microprocessor over a bus. This approach greatly reduces component count.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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