Abstract

AbstractControlling electron tunneling is of fundamental importance in the design and operation of semiconductor nanostructures such as field effect transistors (FETs) and quantum computing device architectures. The exponential sensitivity of tunneling with distance requires precise fabrication techniques to engineer the desired device dimensions to achieve the appropriate tunneling resistances/tunnel rates. This is particularly important for high fidelity spin readout and qubit exchange in quantum computing architectures. Here, it is shown by combining precision fabrication techniques with accurate atomistic modeling, predictive device design criteria are achieved at atomic length scales. Such a tool is useful when devices become more complex or have arbitrary shapes/geometries. In particular, in this study, atomic precision patterning of monolayer degenerately phosphorus‐doped silicon tunnel junctions patterned by scanning tunnelling microscopy lithography and tight‐binding non‐equilibrium Green's function (TB‐NEGF) modeling is combined to describe the dependence of tunnel junction resistance RT on junction length. An agreement with experiment to within a factor of 2 over 4 orders of magnitude in RT is found, and this model allows to accurately determine the barrier height V0 = 57.5 ± 1 meV and lateral seam sxy = 0.39 ± 0.01 nm in these nanoscale junctions. This study confirms the use of the TB‐NEGF formalism to accurately model highly doped atomically precise tunnel junctions in silicon. Further applications of this model will enable improved device performance at the nanoscale.

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