Multi-Gigabit/s OFDM real-time based transceiver engine for emerging 5G MIMO systems

Abstract

This paper presents a highly scalable multi-Gigabit/s Real-Time (RT) Wideband (WB) Orthogonal Frequency Division Multiplexing (OFDM) processing chain for 5G applications. It is aimed to significantly reduce the Hardware (HW) footprint of Multiple Input Multiple Output (MIMO) systems. In this context, implementation complexity results for MIMO configurations of 2 × 2, 4 × 4 and 8 × 8, enabled at sampling rates of 245.76, 122.88, 61.44 and 30.72 MHz, respectively, are compared with the ones from conventional MIMO architectures. For example, for a 8 × 8 MIMO–OFDM configuration implementation, savings of up to 87% are achieved when compared with conventional design methods, in terms of DSP48E1 slices. Moreover, in a Xilinx Virtex 7 XC7VX485T, it is shown that a second processing branch might be implemented, leading to a 5 Gbps (using 1024 Quadrature Amplitude Modulation (QAM)) Single-Input Single-Output (SISO) link or a 16 × 16 MIMO configuration. Finally, in order to validate the proposed architecture, the impact of its inclusion on a complete Field Programmable Gate Array (FPGA) 8 × 8 OFDM system, at LTE’s highest sampling rate of 30.72 MHz, is evaluated. Subsequently, it is demonstrated that this does not affect the performance of OFDM, even in the presence of Carrier Frequency Offset (CFO).