Multi-CMP system with data communication on the fly

Abstract

The paper concerns new solutions for hierarchical Chip Multiprocessor (CMP) systems composed of many CMP modules interconnected by a global data exchange network. New architectural solutions for internal module data are presented in the presence of hierarchical data caches in CMP modules. Inside CMP modules, dynamic shared memory core clusters are organized around L1---L2 data cache busses. Such clusters enable a group-oriented data based on reads on the fly to L1 banks of data present on the busses by many cores at a time. Dynamic switching of cores between such L1---L2 busses is done with porting data in core's L1 caches. Together with data reads on the it provides a very efficient intercluster communication on the fly, especially useful for transfers of strongly shared data. It provides fast cache to cache group data transmissions and eliminates standard transactions based on shared memory in the system. Comparative experimental results based on automatic scheduling of program data flow graphs and execution in a simulator of the proposed architecture evaluate the assumed architectural solutions. The multi-CMP system structure is assessed while taking into account technological limitations of the size of the single CMP module.