Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

Abstract

This work describes voting feedback circuits for triple modular redundant (TMR) self-correcting flip-flops that reduce the flip-flop circuit area by 20% and the energy consumption by 10% over the conventional use of a majority gate. A fully pipelined 256-bit key and 128-bit data advanced encryption standard (AES) engine implemented at the 90 nm technology node using the proposed design and has a maximum performance of 400 MHz and 297 mW in TMR and multi-thread modes. It operates in a low-power, non-redundant mode at 102 mW power dissipation. Testability modes are are also described.