Motion Compensation Memory Access Optimization Strategies for H.264/AVC Decoder

Abstract

H.264/AVC is the latest standard for video coding drafted jointly by the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group. H.264/AVC provides up to 50% gain in compression efficiency over a wide range of bit rates and video resolutions compared to previous standards. On the other hand, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 visual simple profile. In VLSI implementations of the H.264/AVC decoder, off-chip memory access is the main time and power consuming operation, and the motion compensation module is the main memory access bottleneck. This paper proposes four optimization strategies to reduce memory access data cycles and improve memory data bus utilization. Experimental results show that about 60% data cycle reduction can be achieved and more than 20% memory data bus utilization can be improved by these strategies over typical test sequences.