Abstract
We present a fabrication technique for single electron tunnel junctions in silicon. Based on Bonded and Etched back Silicon On Insulator (BESOI) material with a very thin silicon top layer tunnel junctions are realized by electron beam lithography (EBL) in combination with a two-layer resist system. The pattern is transferred by anisotropic reactive ion etching (RIE). The lateral dimensions are reduced further by thermal oxidation in a subsequent step. The process technology is, apart from the e-beam lithography, fully MOS compatible. Different samples with four tunnel junctions in series were characterized at 6 K. The I/U-characteristics reveals a Coulomb blockade as well as a Coulomb staircase, which can be attributed to the asymmetrical structure. By realizing a backgate configuration periodic modulations in the source drain current versus the gate voltage have been measured.
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