Abstract
A detailed theoretical calculation of MOS threshold voltages was carried out in terms of the fixed bulk and total oxide charges, and the difference in work function between the metal and semiconductor. In addition, upper and lower limits on device dimensions, which are related to the characteristics of the fabrication processes used and the saturation level of carriers in the channel, were determined. Devices were then fabricated on (100) silicon substrates, which were selected on the basis of the theoretical calculations. Device types included p- and n-channel enhancement mode, n-depletion mode, and complementary MOS-FET devices. The experimental terminal characteristics of these devices were in good agreement with the theory. Bias temperature stability tests were carried out on the devices at 250°C and a bias potential of ± 10 V. The test results were compared with those obtained for other passivation methods.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
