Abstract
A new technique for modelling the conductance of an MOS device for the electrical logic simulation (the Elogic algorithm) of CMOS circuits is proposed. The technique is general and applicable to any analytic device current model. The Elogic algorithm allows the representation of a logic transition using a finite number of voltage steps and calculates time for each transition between the adjacent voltage steps. The examples show that the new technique can correctly predict a complete electrical waveform with a large voltage step of 1 V to yield at least an order of magnitude computational time advantage over the circuit simulation.
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