Abstract

The manufacture process and the electrical characterization of MOS devices fabricated by wet oxidation of N + implanted n-type 4H–SiC are here presented. Different implantation fluence and energy values were used with the aims to study the effect of the N concentration both at the SiO 2/SiC interface and within the SiO 2 film. High doses, able to amorphise a surface SiC layer to take advantage of the faster oxidation rate of amorphous with respect to crystalline SiC, were also evaluated. The electrical quality of the SiO 2/SiC system was characterized by capacitance–voltage measurements of MOS capacitors. The analyses of the collected data show that only the implanted N which is located at the oxide–SiC interfaces is effective to reduce the interface states density. On the contrary, the interface states density remains high (the same of an un-implanted reference sample) when the implanted N is completely embedded in the region consumed by the oxidation. Furthermore, none generation of fixed positive charges in the oxide was found as a consequence of the different N concentrations enclosed in the oxide films. These results were independent of the amorphisation of the implanted layer by the N + ions. Our results demonstrate that by using a suitable N ion implantation and an appropriate wet oxidation treatment, it is possible to obtain a reduced thermal budget process able to decrease the interface state density near the conduction band edge. The proposed approach should be interesting for the development of the MOSFET technology on SiC.

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