Abstract

Abstract Direct wafer bonding is getting a standard and essential process in high density 3D integration devices. In this study, we investigated impact of direct bonding interface and extremely thinned Si on dicing and thinning processes. By comparing single wafer and direct bonded wafer having extreme thinned Si on top, bigger frontside chippings are observed after dicing for the case of direct bonded wafer. However, cross-sectional images unveil that the initiated point of the chipping is at the interface between SiCN and SiO2, not at the bonding interface. It indicates that direct bonding interface and 5 μm Si are not the root-cause of the chippings. For the backside thinning process, comprehensive analysis including atomic scale vacancy measurement/observation and macro level roughness/morphology analysis are executed. The major impact on die strength was given by macro level roughness. Despite having bigger chipping on bonded wafer, higher die strength is obtained from bonded wafer. It might be due to the stress buffering caused by bonding interface.

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