Abstract

Spiking neural networks and neuromorphic systems have attracted ever increasing interests recently, due to their high computational efficiency by imitating the functional mechanism of cerebral cortex. However, endowing low-cost neuromorphic chips with real-time high-accuracy on-chip learning plasticity for edge applications is still challenging. In this work, we present a digital edge neuromorphic chip for real-time high-accuracy on-chip multi-layer SNN learning in visual recognition tasks. It employs a hierarchical multi-core architecture, a dynamically reconfigurable array parallelism and a quasi-event-driven scheme to improve processing speed. A prototype chip with a core area of 10.39 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was fabricated using a 65-nm 1P9M CMOS process, and typically achieved a real-time speed of 87 frames/s and a power dissipation of 106 mW at an 83 MHz clock rate when training a 4-layer fully-connected SNN. Our chip attained comparably high recognition accuracies of 96.29%, 84.95%, 86.13%, 85.07% and 100% on the MNIST, Fashion-MNIST, ETH-80, MNIST-DVS and Poker-DVS datasets, respectively, with an energy efficiency of 97 pJ/SOP for learning and 30 pJ/SOP for inference.

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