Abstract
Polished vacancy rich material is used in high volume manufacturing of logic and memory devices. Inherent to the crystal pulling process of these materials are voids in the silicon crystal causing trench-based failure in dynamic random access memory (DRAM) chips. The number of failures per die was observed to grow with decreasing feature size. The purpose of the simulation model presented in this report is to quantify the number of these failures for future DRAM generations and thus to gain information about future material related requirements. © 2005 The Electrochemical Society. All rights reserved.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
