Abstract
This work aims at discussing the development of monolithic active pixel sensors (MAPS), which are considered as possible candidate detectors for the inner lay- ers at the future large colliders. In such devices the triple well option, available in deep submicron CMOS technologies, is exploited to implement analog and digital signal processing at the pixel level. In this scheme, the charge collect- ing electrode is laid out using a deep n-well (DNW) and a full readout chain for capacitive detectors is integrated in the elementary cell. In particular, this work is concerned with the design and performance of DNW monolithic sensor prototypes fabricated in a 130 nm CMOS technology, including different test structures and performing pixel-level charge amplification, shaping and data sparsification.
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