Abstract

This paper will discuss the design criteria and characterization results of a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named SDR0 (Sparsified Digital Readout), for the first time we implemented a sparsification logic at the pixel level.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.