Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets

Abstract

Sensitivity-based methods for wire sizing have been shown to be effective in reducing clock skew in routed nets. However, lack of efficient sensitivity computation techniques and excessive space and time requirements often limit their utility for large clock nets. Furthermore, most skew reduction approaches work in terms of the Elmore delay model and, therefore, fail to balance the signal slopes at the clocked elements. In this paper, we extend the sensitivity-based techniques to balance the delays and signal-slopes by matching several moments instead of just the Elmore delay. As sensitivity computation is crucial to our approach, we present a new path-tracing algorithm to compute moment sensitivities for RC trees. Finally, to improve the runtime statistics of sensitivity-based methods, we also present heuristics to allow for efficient handling of large nets by reducing the size of the sensitivity matrix.