Moment based delay modelling for on-chip RC global VLSI interconnect for unit ramp input

Abstract

The Elmore delay has been the metric of choice for the performance driven design applications. But the accuracy of the Elmore delay is insufficient. This paper presents an accurate and efficient model to compute the delay metric of on-chip high speed VLSI interconnects for ramp inputs. The proposed delay metric is based on the distributed RC interconnect model. For optimization like physical synthesis and static timing analysis, efficient interconnect delay computation is critical. In this paper, a delay metric using RC-out has been formulated which computes the delay at the output node. The proposed model is based on the first three moments of the impulse response. Two pole RC model is developed based on the first, second and third moments' effect onto the delay calculation for interconnect lines. This two pole approach permits the pre-characterization of the interconnect delay. The empirical D3M metric is shown to be a typical case. The proposed metric also provides an expression for impulse response. The SPICE simulation results justify the accuracy and efficacy of the proposed model.