Module miniaturization by ultra thin package stacking

Abstract

The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 µm in order to constrain the package thicknesses to a maximum of 100 µm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 µm. In this case 20 µm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20–30 µm and final package thickness is in the range of 60 µm.