Module allocation for on-line testing

Abstract

This article presents a module allocation technique for the synthesis of on-line (concurrent) testable data path from a given scheduled data flow graph. The modules are considered as multi-type, to which more than one type of operation is assigned. The on-line testing is carried out by capturing selective input and output variables of a circuit under test in time frames called passes. The captured variables are shifted out serially to a testing unit, where verification is carried out. An error is detected if any discrepancy is found. The objective is to test each module of the circuit under test for all types of operations assigned to the module. The testing time can be reduced by minimizing the number of variables needed to be shifted out to test all modules. The module allocation is performed with the objective of minimizing the number of modules and the number of variables needed to test these modules. A graph-oriented approach has been employed. Our technique is implemented on different benchmark examples, and the results show an improvement in the testing time, while requiring the minimal number of modules for synthesis.