Abstract
Although SnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanofibers (NFs) are one of the good candidates as active materials for next-generation consumable electronics, these NFs based devices still suffer from insufficient on-off current ratios, large and negative threshold voltages ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>TH</b></sub> ), leading to high energy consumption and rather complicated circuit design. Here, SnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> NFs field-effect transistors (FET) were fabricated by an electrospinning technique. The device performance can be precisely manipulated by controlling the crystal grain size in the NFs. This is done by simply adjusting the annealing holding time to achieve high-performance enhancement mode. For the optimal annealing holding time of 60 min, the grain size of NFs is about 11 nm, and the devices exhibit the best electrical performance, including a small and positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (≈ 2.2 V), a large switching current ratio (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ≥ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> ), and proper carrier mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> ) (≈ 2.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ). Moreover, this approach is universal and can be applied to optimize other metal oxide semiconductors such as ZnO NFs. This simple and facile method indicates that adjusting annealing holding time is a potential way to control the grain size to achieve low voltage operation and enhancement mode 1D metal oxide FETs.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
