Modular systolic array implementation for separable denominator 2‐D block state‐space digital filters based on reduced‐dimensional decomposition

Abstract

Recent advances in integrated circuit technology and digital communication networks have led to increased demand for efficient, high-quality conversion, transmission, and coding of high-resolution images. Accordingly, a highly parallel two-dimensional digital filtering system based on an efficient parallel processing algorithm for two-dimensional digital filters is indispensable. In this paper, the problem of realization is treated for a systolic array of separable denominator 2-D block state-space digital filters based on a reduced-dimensional decomposition proposed earlier. A new systolic array is realized in which the circuit area is minimized by interchanging the columns and rows as a method of reducing the delay circuit, thereby making division and modularization possible. For the present realization method, a three-dimensional configuration is proposed to facilitate local communications. Finally, the performance of the present realization method is evaluated, and its effectiveness is demonstrated. © 1999 Scripta Technica, Electron Comm Jpn Pt 3, 83(2): 55–66, 2000