Modular Synthesis of Timed Circuits using Partial Orders on LPNs

Abstract

This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. Each timed circuit module is specified using a level-ruled Petri net (LPN), a new type of Petri net that allows timing constraints and Boolean level expressions to be annotated between each place and transition. The algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single order on independent enabled transitions. This approach better manages the state explosion problem resulting in a more than an order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than previously possible.