Modular arithmetic decision procedure with auto-correction mechanism

Abstract

In this paper we present an efficient decision procedure which can deal with modulo equivalence based on Horner-Expansion-Diagram (HED) as a canonical decision diagram in order to prove the equivalence of an AND-INVERTER-GRAPH (AIG) representation as the implementation against a polynomial expression over Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2n</sub> as the specification. In other words, even if the implemented polynomials are different in representation, we are able to automatically check their equivalence to the given AIG under modulo equivalence. Furthermore, if the two models are not equivalent, our decision procedure is able to automatically correct the AIG according to the specification. This decision procedure can be used as a theory for SMT solvers targeting non-linear arithmetic circuits. We evaluate our approach on several large arithmetic circuits thereby showing performance benefits of many orders of magnitude than widely accepted industrial techniques.