Modified test generation methods for synchronous sequential circuits

Abstract

The test generation process for synchronous sequential circuits is a complex problem. The overall objective is to obtain an optimum balance between power, area requirements and test generation time. Most of the algorithms use random pattern generators such as Linear Feedback Shift Register (LFSR). However the LFSR can be modified to produce the test patterns according to the Circuit under Test (CUT). Such deterministic patterns are used as input to form a modified synchronization profile of CUT and the minimal observation time is computed. The second modified test generation process uses partitioning of circuits. The partitioned cones are used as modified inbuilt LFSR. Experimental results show that both the modified methods help in improving fault coverage. The experimental results show that modified partitioning method produces fault coverage up to 98% for most benchmark circuits and a compression ratio of 90% can also be achieved.