Abstract
A low power dynamic comparator for Successive Approximation (SAR) analog-to-digital converter (ADC) is presented. The modified dynamic comparator is designed to be implemented in the ultra-low power Successive Approximation Analog to Digital Converter (SAR ADC). The improved comparator has advantages of smaller resolution and stable output voltage for SAR ADC operation by using modified SR Latch compared to previous works reported. The proposed dynamic comparator is designed and simulated in the 0.18 µm CMOS process. Simulation results show that it only consumed 191 pW at 1.5 V power supply with clock frequency of 0.1 MHz. Both pre and post layout has been simulated and the performance analysis is presented.
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