Modified SDF Architecture for Mixed DIF/DIT FFT

Abstract

In this paper, we propose the modified single-path delay feedback (SDF) architecture for FFT implementation, which implements a mixed decimation-in-frequency (DIF)/decimation-in-time (DIT) FFT algorithm. Since final stage is computed as DIT FFT algorithm and other stages including input stage are computed as DIF FFT algorithm, both input and output data occur in normal order and additional clocks for reordering input or output is not required. This architecture is applied to a 64-point FFT and compared to the radix-4 DIF SDF and radix-4 multi-path delay commutator (MDC) architecture in the context of throughput, latency and hardware complexity. As a result, the proposed architecture has a much lower hardware complexity as compared to the radix-4 MDC while maintaining the same throughput and latency, and it achieves a significantly lower latency compared to the original radix-4 SDF architecture with reasonable hardware complexity increment.