Modified maximum a posteriori decoder architecture for low‐power consumption

Abstract

A modified architecture for minimised power consumption in the maximum a posteriori (MAP) decoder based on retiming for register minimisation is proposed in this study. Retiming for register minimisation technique is introduced in the trellis unit of the MAP decoder. Forward state metric and reverse state metric values are retained till the end of the time scale ‘(k −1)’ to calculate log-likelihood ratio (LLR) value. By applying this technique, the number of registers gets reduced, where the node has several output edges carrying the same signal. Depending on the time scale, memory latches reduces from k[(k − 1)/2] to ‘(k − 1)’ in the LLR unit of MAP decoder. Using this technique, optimised architecture is derived and the authors have achieved the power consumption of 173.2 mW, which is less than 12.21% with the reported values, for K = 5, code rate ½ and time scale k = 4. When forward flip-flop retiming is applied 6.08% clock frequency increased and 5.53% total time delay reduced as compared with the register retiming technique.