Modified Decimal Matrix Codes in FPGA configuration memory for multiple bit upsets

Abstract

A novel coding technique is proposed to protect the SRAM based configuration memories against multiple bit upsets (MBU) with minimum redundant bits. The proposed coding technique is based on soft error tolerant Encoder and Decoder. The coding architecture exploits Modified Decimal Matrix Codes (MDMC) to locate and correct soft error present in the memories. The MDMC is typically performed using reconfigurable Array Exclusive-OR Logic (ReAXL) to compute the equivalent decimal addition. The MDMC based on ReAXL can be dynamically reconfigured for both Encoding and decoding and reduces the chip area. The encoder creates the codeword for the original data bits and decoder calculates syndrome vector to confirm the soft error respectively. The proposed MDMC is analyzed and compared to the existing coding techniques such as Decimal Matrix Codes (DMC), Matrix codes (MC) and Hamming Codes. The result shows that the area, power and delay for the proposed MDMC is less compared to the existing coding techniques.