Modification of silicon-on-insulator structures under nano-scale device fabrication

Abstract

Based on the characterization of the ultrathin silicon-on-insulator (SOI) test structures, the effects of charge at the interface between the top silicon layer and the buried oxide (bonded interface) are studied during different technology steps (thinning of the top silicon layer and plasma etching). SOI structures were fabricated by wafer bonding and hydrogen slicing technology. An increase in the charge with the thinning of the top silicon layer and introduction of the mobile charge or the slow interface states after the plasma etching were found for the SOI structures. The conductance oscillations have been observed at room temperature in the ultrathin silicon layers due to formation of tunnel barriers for one type of carriers caused by charge fluctuation.