Models of asynchronous packet-switched multiple and partial multiple bus systems

Abstract

Bus-based systems are very attractive because they are simple and easy to use. Most of the models available in the literature for bus-based systems are for circuit-switched systems. The throughput of a packet-switched system is higher than that of the circuit-switched system due to the fact that in a packet-switched system all the resources can be used at their own speed. Some models of packet-switched multiple bus systems are available in literature [2], where read and write references are treated equally. This means that a processor is blocked after it submits a memory reference, and it is kept in the blocked state until it receives the operand (for a read reference) or an acknowledge signal (for a write reference) from the memory. Some extra throughput can be obtained if the processors are allowed to go back to computation immediately after they submit write references. Stanford's DASH multiprocessor system [20] uses such a technique. This paper shows analytical models to determine the performance of packet-switched multiple and partial multiple bus systems, where the processors are blocked after read references but not after write references. The analytical models have been verified by the simulation models. The results show that when 20% of the memory references are for write operations, 12% more throughput can be achieved if the processors are not blocked after write references.