Modelling of asymmetrical interconnect T-tree laminated on flexible substrate

Abstract

A fast and accurate behavioral modelling of asymmetrical microstrip tree printed on plastic substrate is investigated. The methodology for extracting the asymmetrical tree transfer responses based on the ABCD-matrix analysis is presented. The elements of the interconnect T-tree are constituted by transmission lines (TLs) defined by their characteristic impedance and physical length. The distributed tree network can be assumed as a single input multiple output (SIMO) topology. By considering the circuit equivalent between the electrical path from the tree input and output, the single input single output (SISO) simplified circuit can be established. In order to determine the frequency response of the interconnect tree system, the elementary TLs constituting the tree branches are modelled with their equivalent frequency dependent RLCG network. The novelty of the present paper is the application of the model to the microstrip structure printed on the plastic substrate by analyzing the influence of the metallization conductivity. As proof of concept (POC), a single input and three output distributed interconnect T-tree having branches presented physical lengths from 3 cm to 20 cm was designed. The POC was printed on the Cu metal deposited plastic Kapton substrate. Then, the frequency dependent per unit length resistance, inductance, capacitance and conductance of the elementary branches of the T-tree from DC to 10 GHz were extracted. By implementing the behavioral model of the circuit, the frequency- and time-domain responses of the proposed asymmetrical T-tree are computed. Then, the analyses of the asymmetrical T-tree responses in function of the thin film conductivity of the microstrip interconnect lines were discussed. In addition, time domain analysis enabling to predict the influence of the deposited metallic ink conductivity on the signal integrity is realized by considering a mixed signal corresponding to the digital data “010110000” having 0.5 Gbps rate. Moreover, the signal integrity through the asymmetrical T-tree was also performed with eye diagram. A considerable attenuation and signal delay were occurred due to the roughness and impurities of the copper interconnect ink.