Modelling negative bias temperature instabilities in advanced p-MOSFETs

Abstract

The decrease of the threshold voltage V th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si 3Si (P b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V th shifts are mainly due to the tunnelling of holes at low gate bias | V G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher | V G|. Consequently, device lifetime at operating voltage, based on V th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of SiNSi strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V th shifts in p-MOSFET with Hf y SiO x gate layers and SiO 2/Hf y SiO x gate stacks are simulated, taking into account the generation of P b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO 2/Hf y SiO x gate stacks as compared to single Hf y SiO x layers. This finding is attributed to the beneficial presence of the SiO 2 interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.