Modelling and simulation of integral decoupling capacitors in single and multichip module electronics packaging

Abstract

In high-end packaging structures, switching currents of short pulse width and high clock rate generate significant Delta-I noise which can cause malfunctions of IC circuits. The trend of increasing packing density makes the integral decoupling capacitor preferable than the conventional discrete capacitor. Although integral decoupling capacitors have been proposed and already used in some packaging structures, their electrical performance has not been accurately modeled. This paper presents an efficient and accurate numerical technique for the simulation of Delta-I noise in multi-layer power and ground plane packaging structures containing integral decoupling capacitors. Various factors that determine the effectiveness of integral decoupling capacitors, such as their geometries and locations in packaging structures, are also studied. >