Abstract
This paper presents an approximate analytic model for the performance analysis of a class of multiprocessor based packet switches. For these systems, processors and common memory modules are grouped in clusters, each of them composed of several processor-memory pairs that communicate through a multiple bus interconnection network. Intercluster communication is also achieved using one or more busses. The whole network operates in a circuit-switched mode. After access completion, a processor remains active for an exponentially distributed random time. Access times are also exponential with different means, depending upon the location (local, cluster, external) of the referenced module. The arbitration is done on a priority basis. The performance is predicted by computing the average number of switched packets per time unit. Other related indexes are also given. Numerical results are obtained rather easily by solving a set of two algebraic equations. Simulation is used to validate the accuracy of the approximations used in the model.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
