Abstract
Memory interleaving and multiaccess ports are important details of state-of-the-art supercomputers, by which the powerful CPU is supplied with data at an adequate speed. The data transport will be slowed down and consequently the performance of the CPU will be reduced, if these parallel features of memory organisation cannot be fully exploited, e.g. in case of an unfavorable distribution of data in memory. We present here a model for the memory access of supercomputers, especially vector computers of SIEMENS VP series. The model results in a formula to give quantitative predictions for access times to vector elements with a constant stride. Model parameters are given for the SIEMENS VP series and the theoretical and measured values are compared.
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