Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing

Abstract

This paper models the performance and summarizes the design considerations (electrical, mechanical, and thermal) of CMOS-SOI-NEMS (CMOS Silicon on Insulator nanoelectro mechanical systems) transistors fabricated in the 130-nm technology, which perform as uncooled passive infrared (PIR) sensors. The nanmachined CMOS-SOI-NEMS transistors (dubbed TMOS) are isolated thermally by the postprocessing dry etching with high yield and uniformity, achieved at the wafer-level processing as well as the wafer-level packaging, using 8-in wafers. The TMOS transistor is an active sensor with internal gain achieving voltage, responsivity, over $10^{7}$ V/W. This responsivity is larger by approximately an order of magnitude compared to bolometers, and several orders of magnitude compared to thermopiles or pyros, which are passive devices. The TMOS operates at subthreshold, requiring very low power, of the order of microWatt. Accordingly, this uncooled IR sensor, in the low-cost CMOS-SOI technology, promises to become the standard PIR technology for mobile applications, wearables, and Internet of Things.