Abstract
With technology scaling, a common and efficient strategy to improve the soft error vulnerability of sensitive nodes is to place well/substrate contacts frequently. This paper reports a revised method to integrate the impact of well contacts on SEE response with the bias-dependent SE compact model for circuit simulation. After modifying the SE sub-circuit with resistors and current source placed between the n-well and p-well contacts and then calibrating the parameters by layout-level TCAD simulation results, the resulting model is able to evaluate the SEE vulnerability of devices and circuits with various well contacts. Besides, it is able to evaluate the hardness performance of well contact optimization before fabrication.
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