Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects

Abstract

AbstractThe layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis.