Modeling the Effects of Niobium Surface Roughness on Electrical Conductivity of Nb/Al-AlO$_{x}$/Nb Josephson Junctions

Abstract

Technology Computer Aided Design (TCAD) is being developed for superconductor electronics (SCE). The AlO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{x}$</tex-math></inline-formula> tunnel barriers used in SCE have thicknesses on the order of the surface roughness of sputtered niobium. Surface roughness is not included in a standard CMOS TCAD process simulator and is among the unique modules needed for SCE. An empirical model for surface roughness is developed for TCAD process simulators. This model is merged with the existing sputtering module and coupled with chemical mechanical polishing and aluminum oxidation to generate process-simulated structures of the Nb/Al-AlO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{x}$</tex-math></inline-formula> /Nb junction stack. Electrical simulations of these junctions are used to extract room temperature conductance. The inherent statistical variation of the proposed surface roughness model lends itself to large scale parallel simulation of thousands of junctions. Statistical simulations are performed and statistical analysis is given.