Abstract
This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be used to identify hard-to-test portions of designs, and therefore to devise more cost-effective DFT techniques.
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