Modeling temperature and bias stress effects on threshold voltage of a-Si:H TFTs for gate driver circuit simulation

Abstract

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT) have been important device in modern display panel production. In this paper, we study amorphous silicon thin-film-transistor (TFT) degradation under temperature and bias stresses. Rensselear polytechnic institute (RPI) model is widely used for circuit simulation of a-Si:H TFTs, but the temperature (T = -20 - +65°C) and bias stress effects are not considered in the RPI model. The parameters of sub-threshold in the RPI model with temperature and bias stress effects are explored and formulated with the measured I-V data. The results can be used together with the existing model, and thus can describe the temperature dependent characteristics of a-Si:H TFTs well. A 14 a-Si:H TFTs integrated gate (ASG) driver circuit is simulated and tested using the modified RPI model card. The simulations predict the temperature effect on the dynamic properties of ASG circuit and power consumption.