Abstract
Cell capacitance is a well-known parameter in silicon solar cells. Its effects on the power units, specially on the S3R, is also well known since it has to be taken into account to design them. The capacitor energy is dis-charged into the power switch and the dissipation in-creases. Moreover, it introduces a delay in the energy transfer from the array to the main power bus. In triple junction solar cells, this parasitic element becomes far more complex and is not so well characterized. This paper addresses this issue and proposes a large signal model to be used in combination with a S3R.
Highlights
Junction capacitance is a well-known issue in silicon semiconductors
There are two main contributors to this parasitic effect: -The depletion layer capacitance -The diffusion capacitance The first one is very simple to explain because it has the same concept as a conventional capacitor: two metal plates separated by a dielectric material
In the case of a semiconductor junction (e.g in a silicon diode), the depletion layer between the n- and p-sides of a p–ndiode serves as an insulating region that separates the two diode contacts
Summary
Junction capacitance is a well-known issue in silicon semiconductors. In the case of a semiconductor junction (e.g in a silicon diode), the depletion layer between the n- and p-sides of a p–ndiode serves as an insulating region that separates the two diode contacts. The diode in reverse bias exhibits a depletion-layer capacitance, known as junction capacitance. In forward bias, besides the above depletion-layer capacitance, minority carrier charge injection and diffusion occurs. Typical values for transit time are 0.1–100 ns On this basis, the diffusion capacitance is calculated to be: CD dQD dvD. For usual current levels in forward bias, this capacitance far exceeds the depletion-layer capacitance
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