Modeling of NBTI Kinetics in RMG Si and SiGe FinFETs, Part-I: DC Stress and Recovery

Abstract

An ultrafast (10- $\mu \text{s}$ delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift ( $\Delta {V}_{T}$ ) in replacement metal gate-based high-K metal gate Si and SiGe p-FinFETs. The dc stress-recovery $\Delta {V}_{T}$ time kinetics, voltage acceleration factor (VAF), and temperature activation energy ( ${E}_{A}$ ) are compared for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate-stack. A comprehensive physical model framework based on uncorrelated contributions from the generation of interface ( $\Delta {V}_{\mathrm {IT}}$ ) and bulk oxide ( $\Delta {V}_{\mathrm {OT}}$ ) traps and hole trapping in preexisting defects ( $\Delta {V}_{\mathrm {HT}}$ ) is used to explain the measured data. The impact of Ge% and N% on $\Delta {V}_{T}$ , VAF, ${E}_{A}$ , temperature (T) dependence of VAF, and stress bias ( ${V}_{\mathrm {GSTR}}$ ) dependence of ${E}_{A}$ are quantified. The interface trap generation component is independently verified by direct-current ${I}$ – ${V}$ (DCIV) measurements.