Modeling of High Voltage MOSFETs Based on EKV (HV-EKV)

Abstract

The accurate compact modeling of High Voltage (HV) MOS transistors has always been a great challenge in the device modeling community. This is due to the fact that the charges and field associated with the drift region and intrinsic MOS have very complex dependence on the external terminal biases owing to the asymmetric device architecture. In this chapter, A modeling strategy for HVMOS transistors (HV-EKV) based on the scalable drift resistance [1, 2] and the use of charge based EKV2.6 MOSFET model [3] as a core for the intrinsic MOS channel is presented [4, 5]. The strategy is optimized according to the fast convergence and good accuracy criteria. The model is stable and robust in the entire bias range useful for circuit design purpose. An important aspect of this general model is the scalability of the model with physical and electrical parameters along with the correct modeling of quasi-saturation and self-heating effect. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS [6] and VDMOS [7] devices, and tested on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), HSpice (Synopsys), Spectre (Cadence) and UltraSim (Cadence). The model shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. Also the model exhibits excellent scalability with transistor width, drift length, number of fingers and temperature. The last part of this chapter will explain the importance of modeling of lateral non-uniform doping in the intrinsic channel [8, 9, 10, 11]. It is shown that C GD & C DG capacitances are strong function of lateral doping [11, 12].