Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

Abstract

SUMMARYThis work presents high‐frequency noise measurements and compact modeling for a 90‐nm silicon complementary metal–oxide–semiconductor (CMOS) technology in terms of radio frequency (RF) figures of merit (FoMs). Minimum noise figure (NFmin), equivalent noise resistance (Rn), optimum source reflection coefficient (Γopt), thermal noise excess factor and a recently introduced FoM for common‐source low‐noise amplifier (LNA) design are presented from a circuit design perspective. For this purpose, the behavior of the above mentioned RF FoMs is investigated over the level of channel inversion, providing insight from a circuit design point of view. The EKV3 MOSFET advanced compact model has been used in Spectre simulator, and results are validated over a large range of frequencies, channel lengths and bias points, for both N‐type and P‐type MOS devices. Optimum performance is shown to be shifted from higher to lower levels of inversion in moderate inversion, when scaling from 240 nm down to 100 nm. This is of great significance considering that the demand for low‐power RF circuits becomes more and more imperative, as planar silicon CMOS technology is scaled to the deca‐nanometer regime. Copyright © 2014 John Wiley & Sons, Ltd.