Abstract
Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. In this paper, we first propose a piece-wise linear (PWL) model for the far-end response of a CPW considering ramp input and capacitive loading. The PWL model has a high accuracy but uses at least 1000x less time compared to SPICE. We then apply the PWL model to synthesize the CPW geometry for clock trees considering constrains of rising time and oscillation at sinks. We obtain a spectrum of solutions with smooth tradeoff between area and power.
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