Modeling of Analog-Digital Loops in VHDL

Abstract

The previous chapters introduced the engineer to some of the basic concepts in using VHDL for behavioral modeling. This chapter is written to assist the applications engineer familiar with Automatic Gain Control (AGC) and Phase-Locked (PL) loops in applying those concepts. The intention is to incorporate loop behavior into analogdigital modeling and demonstrate the resulting analog-digital simulation. Described is an approach for modeling combined analog-digital loop behavior -- centered on the VHDL behavioral models used to simulate the AGC and PL loops. This approach enables the VHDL simulation of mixed analog-digital hardware designs incorporating these control loops.